In a semiconductor device having a plurality of MOS (Metal Oxide Semiconductor) transistors integrated therein, a shallow trench isolation (STI) is used for element isolation. Since silicon used in an active region of an MOS transistor is different in thermal expansion coefficient from an oxide film used in the STI, stress is produced in an MOS transistor provided near the STI. With the progress of reduction in size of MOS transistors, fluctuations in properties of the MOS transistors caused by this STI stress have become a problem. Specifically, the mobility increases due to the STI stress (compressive stress) in the case of a P-type MOS transistor, while the mobility decreases due to the STI stress (compressive stress) in the case of an N-type MOS transistor (refer to, for example, R. A. Bianchi et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance”, IEEE, IEDM Proc., pp. 117-120, 2002 (NPD 1)).
As a technique for reducing such STI strain, there has been known a technique disclosed in Japanese Patent Laying-Open No. 2008-288268 (PTD 1), for example. In a semiconductor integrated circuit described in this document, an off-state dummy transistor is disposed adjacent to an active region of an MOS transistor involved in circuit operation. As a result, stress strain to the MOS transistor is reduced.
In a technique disclosed in International Publication No. WO2009/037808 (PTD 2), a substrate contact line is disposed at an outer end of an active region that is on the outer side of the aforementioned dummy transistor, in order to further reduce the STI strain.
Japanese Patent Laying-Open No. 2006-286889 (PTD 3) discloses a technique of enhancing an operating current of an MOS transistor by actively using the STI strain. Specifically, an insulating material that provides compressive stress to an active region of a P-type MOS transistor is filled into a region adjacent to the P-type MOS transistor in a channel length direction thereof, of an STI element isolation region. An insulating material that provides tensile stress to the P-type and N-type MOS transistors is filled into the remaining element isolation region.
A technique of using the aforementioned off-state dummy transistor for element isolation of adjacent MOS transistors has been conventionally known (refer to, for example, Japanese Patent Laying-Open No. 4-125949 (PTD 4) and Japanese Patent Laying-Open No. 11-233640 (PTD 5)).